SH7263 Datasheet, PDF (843/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 16 Synchronous Serial Communication Unit (SSU)
(3) Data Reception
Figure 16.7 shows an example of reception operation, and figure 16.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an SSRXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
During continuous slave reception in SSU mode, read the SS receive data register (SSRDR) before
the next reception operation starts (before the externally connected master device starts the next
transmission). When the next reception operation starts after the receive data full (RDRF) bit in
the SS status register (SSSR) is set to 1 and before SSRDR is read, and SSRDR is read before
reception of one frame completes, the conflict/incomplete error (CE) bit in SSSR is set to 1 after
the reception operation ends. In addition, when the next reception operation starts after RDRF is
set to 1 and before SSRDR is read, and SSRDR is not read before reception of one frame
completes, the receive data is discarded, even though neither the CE bit nor the overrun error
(ORER) bit in SSSR is set to 1.
Rev. 2.00 Mar. 14, 2008 Page 809 of 1824
REJ09B0290-0200