SH7263 Datasheet, PDF (890/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
SCL
SDA
(Input)
MST
1
2
Bit 0 Bit 1
7
8
1
Bit 6 Bit 7 Bit 0
7
8
1
2
Bit 6 Bit 7 Bit 0 Bit 1
TRS
RDRF
ICDRS
Data 1
Data 2
Data 3
ICDRR
Data 1
User
[2] Set MST
processing
(when outputting the clock)
[3] Read ICDRR
Figure 17.15 Receive Mode Operation Timing
Data 2
[3] Read ICDRR
SCL
SDA
(Input)
MST
RCVD
BC2 to BC0
1
2
3
4
5
6
7
8
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
000
111 110 101 100 011 010 001 000
[2] Set MST
[3] Set the RCVD bit after checking if BC2 = 1
Figure 17.16 Operation Timing For Receiving One Byte (MST = 1)
Rev. 2.00 Mar. 14, 2008 Page 856 of 1824
REJ09B0290-0200