SH7263 Datasheet, PDF (440/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
10.3.7 DMA Reload Transfer Count Registers (RDMATCR)
The DMA reload transfer count registers (RDMATCR) are 32-bit readable/writable registers.
When the SAR/DAR reload function is enabled, the RDMATCR value is written to the transfer
count register (DMATCR) at the end of the current DMA transfer. In this case, a new value for the
next DMA transfer can be preset in RDMATCR during the current DMA transfer. When the
SAR/DAR reload function is disabled, RDMATCR is ignored.
The upper eight bits of RDMATCR are always read as 0, and the write value should always be 0.
As in DMATCR, the transfer count is 1 when the setting is H'00000001, 16,777,215 when
H'00FFFFFF is set, and 16,777,216 (the maximum) when H'00000000 is set. To transfer data in
16 bytes, one 16-byte transfer (128 bits) counts one.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Initial value:
R/W:
15
-
0
R/W
14
-
0
R/W
13
-
0
R/W
12
-
0
R/W
11
-
0
R/W
10
-
0
R/W
9
-
0
R/W
8
-
0
R/W
7
-
0
R/W
6
-
0
R/W
5
-
0
R/W
4
-
0
R/W
3
-
0
R/W
2
-
0
R/W
1
-
0
R/W
0
-
0
R/W
Rev. 2.00 Mar. 14, 2008 Page 406 of 1824
REJ09B0290-0200