SH7263 Datasheet, PDF (1818/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
Page Revision (See Manual for Details)
8.1 Features
211
Description amended
• Way lock function (operand cache only): Way 2 and way 3
are lockable
8.1.1 Cache Structure
Description amended
Each of the address and data sections is divided into 128
entries per way. …
8.3.2 Read Access
222
Description added
(2) Read Miss
… The write-back unit is 16 bytes. Cache updates and write-
backs to memory are performed in wrap-around fashion. For
example, if the value of the lower four bits of an address that
triggers a read miss is H'4, the value of the lower four address
bits changes from H'4 to H'8, H'C, and H'0, in that order, when
cache updates or write-backs are performed.
8.3.4 Write Operation 223
(Only for Operand
Cache)
(2) Write Miss
Description added
… The write-back unit is 16 bytes. Cache updates and write-
backs to memory are performed in wrap-around fashion. For
example, if the value of the lower four bits of an address that
triggers a write miss is H'4, the value of the lower four address
bits changes from H'4 to H'8, H'C, and H'0, in that order, when
cache updates or write-backs are performed.
8.4.1 Address Array 226, 227 Description added
(2) Address-Array Write
(Non-Associative
Operation)
… When 0 is written to the V bit, 0 must also be written to the
U bit of that entry. When memory write-backs are performed,
the value of the lower four address bits changes from H'0 to
H'4, H'8, and H'C, in that order.
(3) Address-Array Write 227
(Associative Operation)
Description added
… However, when 0 is written to the V bit, 0 must also be
written to the U bit of that entry. When memory write-backs are
performed, the value of the lower four address bits changes
from H'0 to H'4, H'8, and H'C, in that order.
9.4.2 CSn Space Bus 245
Control Register
(CSnBCR) (n = 0 to 7)
Note added
Bit
Bit Name
11
ENDIAN
Initial
Value
0
R/W Description
R/W Endian Setting
Specifies the arrangement of data in a space.
0: Arranged in big endian
1: Arranged in little endian
Note: Area 0 cannot be set to little endian mode. In
the case of area 0, this bit is always read as 0,
and the write value should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1784 of 1824
REJ09B0290-0200