SH7263 Datasheet, PDF (451/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Choose to detect DREQ by either the edge or level of the signal input with the DL and DS bits in
CHCR_0 to CHCR_3 as shown in table 10.6. The source of the transfer request does not have to
be the data transfer source or destination. When DREQ is detected by a rising/falling edge and
DMA transfer is performed in burst mode, the transfer continues until DMATCR reaches 0 by one
DMA transfer request. In cycle steal mode, one DMA transfer is performed by one request.
Table 10.6 Selecting External Request Detection with DL and DS Bits
DL Bit
0
1
CHCR
DS Bit
0
1
0
1
Detection of External Request
Low-level detection
Falling-edge detection
High-level detection
Rising-edge detection
When DREQ is accepted, the DREQ pin enters the request accept disabled state (non-sensitive
period). After issuing acknowledge DACK signal for the accepted DREQ, the DREQ pin again
enters the request accept enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
Overrun 0: Transfer is terminated after the same number of transfer has been performed as
requests.
Overrun 1: Transfer is terminated after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 10.7 Selecting External Request Detection with DO Bit
CHCR
DO Bit
0
1
External Request
Overrun 0
Overrun 1
Rev. 2.00 Mar. 14, 2008 Page 417 of 1824
REJ09B0290-0200