SH7263 Datasheet, PDF (1557/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 30 I/O Ports
30.3.2 Port B Data Register L (PBDRL)
PBDRL is a 16-bit readable/writable register that stores port B data. The PB12DR to PB0DR bits
correspond to the PB12/WDTOVF/IRQOUT/REFOUT/UBCTRG to PB0/SCL0/PINT0/IRQ0
pins, respectively.
When a pin function is general output, if a value is written to PBDRL, that value is output directly
from the pin, and if PBDRL is read, the register value is returned directly regardless of the pin
state.
When a pin function is general input, if PBDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PBDRL, although that value is written into PBDRL, it
does not affect the pin state. Table 30.4 summarizes PBDRL read/write operations.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 0
0
0
0
0
0
0
0
*
*
*
*
*
*
*
*
R/W: R
R
R R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Note: * Depends on the state of the external pin.
Initial
Bit
Bit Name Value R/W
15 to 13 —
All 0
R
12
PB12DR 0
R/W
11
PB11DR 0
R/W
10
PB10DR 0
R/W
9
PB9DR 0
R/W
8
PB8DR 0
R/W
7
PB7DR Pin state R
6
PB6DR Pin state R
5
PB5DR Pin state R
4
PB4DR Pin state R
3
PB3DR Pin state R
2
PB2DR Pin state R
1
PB1DR Pin state R
0
PB0DR Pin state R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
See table 30.4.
Rev. 2.00 Mar. 14, 2008 Page 1523 of 1824
REJ09B0290-0200