SH7263 Datasheet, PDF (808/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
• Receiving Serial Data (Clock Synchronous Mode)
Figures 15.15 and 15.16 show sample flowcharts for receiving serial data. When switching
from asynchronous mode to clock synchronous mode without SCIF initialization, make sure
that ORER, PER, and FER are cleared to 0.
Start of reception
Read ORER flag in SCLSR
ORER = 1?
Yes
[1]
[1] Receive error handling:
Read the ORER flag in SCLSR to identify
any error, perform the appropriate error
handling, then clear the ORER flag to 0.
Reception cannot be resumed while the
ORER flag is set to 1.
No
Error handling
[2] SCIF status check and receive data read:
Read SCFSR and check that RDF = 1,
Read RDF flag in SCFSR
[2]
then read the receive data in SCFRDR,
and clear the RDF flag to 0. The transition
of the RDF flag from 0 to 1 can also be
No
RDF = 1?
identified by a receive FIFO data full
interrupt (RXI).
Yes
Read receive data in
SCFRDR, and clear RDF
[3]
flag in SCFSR to 0
No
All data received?
Yes
Clear RE bit in SCSCR to 0
End of reception
[3] Serial reception continuation procedure:
To continue serial reception, read at least
the receive trigger set number of receive
data bytes from SCFRDR, read 1 from the
RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in
SCFRDR can be ascertained by reading
SCFRDR. However, the RDF bit is
cleared to 0 automatically when an RXI
interrupt activates the DMAC to read the
data in SCFRDR.
Figure 15.15 Sample Flowchart for Receiving Serial Data (1)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 15.16 Sample Flowchart for Receiving Serial Data (2)
Rev. 2.00 Mar. 14, 2008 Page 774 of 1824
REJ09B0290-0200