SH7263 Datasheet, PDF (467/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
(4) Bus Mode and Channel Priority
In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a
request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0
will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer
on channel 1 will only resume on completion of the transfer on channel 0.
When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the
higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing
the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1,
channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is
replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of
this is shown in figure 10.12.
When multiple channels are in burst mode, data transfer on the channel that has the highest
priority is given precedence. When DMA transfer is being performed on multiple channels, the
bus mastership is not released to another bus-master device until all of the competing burst-mode
transfers have been completed.
CPU
DMA
CH1
DMA
CH1
DMA
CH0
CH0
DMA
CH1
CH1
DMA
CH0
CH0
DMA
CH1
DMA
CH1
CPU
CPU
DMAC CH1
Burst mode
DMAC CH0 and CH1
Cycle steal mode
DMAC CH1
Burst mode
CPU
Priority: CH0 > CH1
CH0: Cycle steal mode
CH1: Burst mode
Figure 10.12 Bus State when Multiple Channels are Operating
In round-robin mode, the priority changes as shown in figure 10.3. Note that channels in cycle
steal and burst modes must not be mixed.
Rev. 2.00 Mar. 14, 2008 Page 433 of 1824
REJ09B0290-0200