SH7263 Datasheet, PDF (1847/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Index
Numerics
16-bit/32-bit displacement ........................ 51
A
A/D conversion time
(multi mode and scan mode)................. 1170
A/D conversion time (single mode)...... 1169
A/D conversion timing ......................... 1169
A/D converter (ADC) ........................... 1151
A/D converter activation......................... 593
A/D converter characteristics................ 1767
A/D converter start request delaying
function................................................... 586
Absolute address....................................... 51
Absolute address accessing....................... 51
Absolute maximum ratings................... 1683
AC characteristics................................. 1693
AC characteristics measurement
conditions ............................................. 1766
Access size and data alignment .............. 289
Access wait control................................. 301
ADC timing .......................................... 1749
Address array.................................. 212, 226
Address array read .................................. 226
Address errors......................................... 127
Address map ........................................... 236
Address multiplexing.............................. 312
Address spaces
of on-chip high-speed RAM ................. 1547
Address spaces
of on-chip RAM for data retention ....... 1547
Address-array write
(associative operation) ............................ 227
Address-array write
(non-associative operation)..................... 226
Addressing modes..................................... 52
Analog input pin ratings ....................... 1175
AND/NAND flash memory controller
(FLCTL)................................................ 1185
Arithmetic operation instructions.............. 71
Automatic decoding stop function ........ 1139
Auto-refreshing ....................................... 339
Auto-request mode.................................. 416
B
Bank active ............................................. 332
Banked register and input/output
of banks................................................... 181
BCHG interrupt..................................... 1321
BEMP interrupt..................................... 1315
Bit manipulation instructions .................... 82
Bit synchronous circuit ........................... 863
Branch instructions ................................... 76
BRDY interrupt..................................... 1308
Break detection and processing............... 779
Break on data access cycle...................... 204
Break on instruction fetch cycle.............. 203
Buffer memory...................................... 1329
Buffering format ................................... 1140
Bulk transfers........................................ 1348
Burst mode.............................................. 431
Burst MPX-I/O interface......................... 366
Burst read................................................ 324
Burst ROM (clocked asynchronous)
interface .................................................. 352
Burst ROM (clocked synchronous)
interface .................................................. 371
Burst write............................................... 329
Bus arbitration......................................... 379
Bus format for SSI module ..................... 884
Bus state controller (BSC) ...................... 231
Bus timing............................................. 1701
Bus-released state...................................... 85
Rev. 2.00 Mar. 14, 2008 Page 1813 of 1824
REJ09B0290-0200