SH7263 Datasheet, PDF (1090/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
Initial
Bit
Bit Name Value R/W Description
5
RXF
0
R/(W)* Receive Normal Completion
Indicates that data for the number of bytes specified by
the message length bits has been received normally.
[Setting condition]
• When data for the number of bytes specified by the
message length bits has been received normally.
[Clearing condition]
• When 1 is written
4
RXEDE
0
R/(W)* Broadcast Receive Error
Indicates that data could not be received because the
receive buffer is not in the receive enabled state (when
the RE bit is not set to 1 or the RXBSY flag is set.)
during receiving control field broadcast reception. This
bit functions when the DEE bit in IECTR is set to 1.
[Setting condition]
• When data could not be received during broadcast
reception.
[Clearing condition]
• When 1 is written
3
RXEOVE 0
R/(W)* Receive Overrun Flag
Used to indicate the overrun during data reception. The
IEB sets this flag when the IEB receives the next byte
data while the receive data has not been read (the
RXBSY flag is not cleared). If this case, the IEB
assumes that an overrun error has occurred and
returns a NAK to the communications destination unit.
The communications destination unit retransmits data
up to the maximum number of transmit bytes. The IEB,
however, returns a NAK when the RXBSY flag remains
set.
If the RXBSY flag is cleared to 0, the IEB returns an
ACK, and receives the next data.
In broadcast reception, if the RXBSY flag is set during
data receive start, the IEB immediately enters the wait
state. This flag becomes enabled only after the receive
start flag (RXS) is set.
[Setting condition]
• When the next byte data is received while the
RXBSY flag is not cleared.
[Clearing condition]
• When 1 is written
Rev. 2.00 Mar. 14, 2008 Page 1056 of 1824
REJ09B0290-0200