SH7263 Datasheet, PDF (1030/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
If, at any time, a reference message cannot be detected on the CAN Bus, and the cycle time
CYCTR reaches TCMR2, RCAN-TL1 automatically aborts all pending transmissions (including
the Reference Message).
The following is the sequence to request further transmission in Time Triggered mode.
Idle (wait for Time-Trigger)
Update data before next match
of Tx-Trigger Time
Compare match
Mailbox[x] is ready
to be updated for
next transmission
No
Bus Idle?
Yes
Transmission Start
No Arbitration on Bus
Clear TXACK[x]
TXACK[x] = 1 ?
No _{Waiting for}
Interrupt
Yes
IRR8 = 1 ?
No _{Waiting for}
Interrupt
End Of Frame
CAN Bus
Figure 19.21 Message transmission request
S/W has to ensure that a message is updated before a Tx trigger for transmission occurs.
When the CYCTR reaches to TTT (Tx-Trigger Time) of a Mailbox and CCR matches with the
programmed cycle for transmission, RCAN-TL1 immediately transfers the message into the Tx
buffer. At this point, RCAN-TL1 will attempt a transmission within the specified Time Enable
Window. If RCAN-TL1 misses this time slot, it will suspend the transmission request up to the
next Tx Trigger, keeping the corresponding TXPR bit set to ‘1’ if the transmission is periodic
(Mailbox-24 to 30). There are three factors that may cause RCAN-TL1 to miss the time slot –
1. The CAN bus currently used
2. An error on the CAN bus during the time triggered message transmission
3. Arbitration loss during the time triggered message transmission
Rev. 2.00 Mar. 14, 2008 Page 996 of 1824
REJ09B0290-0200