SH7263 Datasheet, PDF (1591/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
Bit
4
3 to 0
Initial
Bit Name Value R/W
MSTP7
0
R/W
⎯
All 0 R
Description
Module Stop 7
When the MSTP7 bit is set to 1, the supply of the clock
to the FPU is halted. After setting the MSTP7 bit to 1,
the MSTP7 bit cannot be cleared by writing 0. This
means that, after the supply of the clock to the FPU is
halted by setting the MSTP7 bit to 1, the supply cannot
be restarted by clearing the MSTP7 bit to 0.
To restart the supply of the clock to the FPU after it was
halted, reset the LSI by a power-on reset.
0: FPU runs.
1: Clock supply to FPU is halted.
Reserved
These bits are always read as 0. The write value should
always be 0.
32.2.3 Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. Only byte access is valid.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit:
Initial value:
R/W:
7
HIZ
0
R/W
6
MSTP
36
1
R/W
5
MSTP
35
1
R/W
4
MSTP
34
1
R/W
3
MSTP
33
1
R/W
2
MSTP
32
1
R/W
1
MSTP
31
1
R/W
0
MSTP
30
0
R/W
Rev. 2.00 Mar. 14, 2008 Page 1557 of 1824
REJ09B0290-0200