SH7263 Datasheet, PDF (1402/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3 Register Configuration
The LCDC includes the following registers. For description on the address and processing status
of these registers, refer to section 34, List of Registers.
Table 26.2 Register Configuration
Register Name
Abbreviation R/W
LCDC input clock register
LDICKR
R/W
LCDC module type register LDMTR
R/W
LCDC data format register
LDDFR
R/W
LCDC scan mode register
LDSMR
R/W
LCDC data fetch start address LDSARU
R/W
register for upper display panel
LCDC data fetch start address LDSARL
R/W
register for lower display panel
LCDC fetch data line address LDLAOR
R/W
offset register for display panel
LCDC palette control register LDPALCR
R/W
Palette data register 00 to FF LDPR00 to R/W
LDPRFF
LCDC horizontal character
LDHCNR
R/W
number register
LCDC horizontal
LDHSYNR R/W
synchronization signal register
LCDC vertical displayed line LDVDLNR R/W
number register
LCDC vertical total line number LDVTLNR
R/W
register
LCDC vertical synchronization LDVSYNR R/W
signal register
LCDC AC modulation signal LDACLNR R/W
toggle line number register
LCDC interrupt control register LDINTR
R/W
LCDC power management
LDPMMR
R/W
mode register
Initial Value Address
H'0101
H'FFFFFC00
H'0109
H'FFFFFC02
H'000C
H'FFFFFC04
H'0000
H'FFFFFC06
H'0C000000 H'FFFFFC08
Access
Size
16
16
16
16
32
H'0C000000 H'FFFFFC0C 32
H'0280
H'FFFFFC10 16
H'0000
⎯
H'4F52
H'FFFFFC12 16
H'FFFFF800 to 32
H'FFFFFBFC
H'FFFFFC14 16
H'0050
H'FFFFFC16 16
H'01DF
H'FFFFFC18 16
H'01DF
H'FFFFFC1A 16
H'01DF
H'FFFFFC1C 16
H'000C
H'FFFFFC1E 16
H'0000
H'0010
H'FFFFFC20 16
H'FFFFFC24 16
Rev. 2.00 Mar. 14, 2008 Page 1368 of 1824
REJ09B0290-0200