SH7263 Datasheet, PDF (1612/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
32.3 Operation
32.3.1 Sleep Mode
(1) Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral
modules continue to run in sleep mode. In modes 0, 1 and 3, continuous clock output from the
CKIO pin can be specified.
(2) Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), a DMA
address error, or a reset (manual reset or power-on reset).
• Canceling by an interrupt
When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and
interrupt exception handling is executed. When the priority level of the generated interrupt is
equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU,
or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt
request is not accepted and sleep mode is not canceled.
• Canceling by a DMA address error
When a DMA address error occurs, sleep mode is canceled and DMA address error exception
handling is executed.
• Canceling by a reset
Sleep mode is canceled by a power-on reset or a manual reset.
Rev. 2.00 Mar. 14, 2008 Page 1578 of 1824
REJ09B0290-0200