SH7760 Datasheet, PDF (990/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

26.3.17 DMA Control Register (DMACR)
DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal.
The DMA request signal is output based on a value that has been set to SET2 to SET0.
Bit: 7
6
5
DMAEN ^-
-
Initial value: 0
0
0
R/W: R/W R R
4
3
2
1
0
-
-
SET2 SET1 SET0
0
0
0
0
0
R R R/W R/W R/W
Bit
Initial
Bit
Name Value R/W
7
DMAEN 0
R/W
6 to 3 
All 0 R
2
SET2 0
R/W
1
SET1 0
R/W
0
SET0 0
R/W
Description
DMA Enable
0: Disables output of DMA request signal.
1: Enables output of DMA request signal.
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Request Signal Assert Condition
Sets DMA request signal assert condition.
000: Not output
001: FIFO remained data is 1/4 or less of FIFO capacity.
010: FIFO remained data is 1/2 or less of FIFO capacity.
011: FIFO remained data is 3/4 or less of FIFO capacity.
100: FIFO remained data is 1 byte or more.
101: FIFO remained data is 1/4 or more of FIFO capacity.
110: FIFO remained data is 1/2 or more of FIFO capacity.
111: FIFO remained data is 3/4 or more of FIFO capacity.
Rev. 1.0, 02/03, page 940 of 1294