SH7760 Datasheet, PDF (330/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

10.6 Operation
10.6.1 Endian/Access Size and Data Alignment
This LSI supports both big-endian mode, in which upper byte in a string of byte data is at an
address 0, and little-endian mode, in which lower byte in a string of byte data is at an address 0.
The mode is specified by the MD5 pin at a power-on reset by the RESET pin. When the MD5 pin
is low, big-endian mode is specified, and when the MD5 pin is high, little-endian mode is
specified.
A data bus width of 8, 16, or 32 bits can be selected for the normal memory interface, 32 bits for
the synchronous DRAM interface, and 8 or 16 bits for the PCMCIA interface. Data alignment is
carried out according to the data bus width and endian mode of each device. Accordingly, when
the data bus width is narrower than the access size, multiple bus cycles are automatically
generated to reach the access size. In this case, access is performed by automatically incrementing
addresses to the bus width. For example, when a long word access is performed at the area with an
8-bit bus width in the SRAM interface, each address is incremented one by one, and then access is
performed four times. In the 32-byte transfer, a total of 32-byte data is continuously transferred
according to the set bus width. The first access is performed on the data for which there was an
access request, and the remaining accesses are performed using wraparound on 32-byte boundary
data. During these transfers, the bus is not released and refresh operation is not performed. In this
LSI, data alignment and data length conversion between different interfaces is performed
automatically. Quadword access is used only in transfer by the DMAC.
The relationships between the endian mode, device data length, and access unit are shown in
tables 10.9 to 10.14.
Rev. 1.0, 02/03, page 280 of 1294