SH7760 Datasheet, PDF (148/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

6. FTRV latency " (L1, L2, L3, L4)/L5": L1 is the latency for FR [n], L2 that for FR [n+1], L3
that for FR [n+2], L4 that for FR [n+3], and L5 that for FPSCR.
7. Latency "L1/L2/L3/L4" of MAC.L and MAC.W instructions: L1 is the latency for Rm, L2
that for Rn, L3 that for MACH, and L4 that for MACL.
8. Latency "L1/L2" of MUL.L, MULS.W, MULU.W, DMULS.L, and DMULU.L instructions:
L1 is the latency for MACH, and L2 that for MACL.
9. Execution pattern: Instruction execution pattern number (see figure 5.2)
10. Lock/stage: Stage locked by the instruction
11. Lock/start: Locking start cycle; 1 is the first D-stage of the instruction.
12. Lock/cycles: Number of cycles locked
Exceptions:
1. When a floating-point computation instruction is followed by an FMOV store instruction,
an STS FPUL, Rn instruction, or an STS.L FPUL, @-Rn instruction, latency of the
floating-point computation is decreased by 1 cycle.
2. When the preceding instruction loads the shift amount of the following SHAD/SHLD,
latency of the load is increased by 1 cycle.
3. When an LS group instruction with latency of less than 3 cycles is followed by a double-
precision floating-point instruction, FIPR, or FTRV, latency of the first instruction is
increased to 3 cycles.
Example: In the case of FMOV FR4,FR0 and FIPR FV0,FV4, FIPR is stalled for 2
cycles.
4. When MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/DMULS.L/DMULU.L is followed by an
STS.L MACH/MACL, @-Rn instruction, latency of MAC.W/MAC.L/MUL.L/MULS.W/
MULU.W/DMULS.L/DMULU.L is 5 cycles.
5. In the case of consecutive executions of MAC.W/MAC.L/MUL.L/MULS.W/MULU.W/
DMULS.L/DMULU.L, latency is decreased to 2 cycles.
6. When an LDS to MACH/MACL is followed by an STS.L MACH/MACL, @-Rn
instruction, latency of the LDS to MACH/MACL is 4 cycles.
7. When an LDS to MACH/MACL is followed by MAC.W/MAC.L/MUL.L/MULS.W/
MULU.W/DMULS.L/DMULU.L, latency of the LDS to MACH/MACL is 1 cycle.
8. When an FSCHG or FRCHG instruction is followed by an LS group instruction that
reads from or writes to a floating-point register, the aforementioned LS group
instructions cannot be executed in parallel.
9. When a single-precision FTRC instruction is followed by an STS FPUL, Rn instruction,
latency of the single-precision FTRC instruction is 1 cycle.
Rev. 1.0, 02/03, page 98 of 1294