SH7760 Datasheet, PDF (374/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(11) Changing the Burst Length
When synchronous DRAM is connected to this LSI with a 32-bit memory bus width, a burst
length of either 4 or 8 is specifiable with the SDBL bit in BCR3. For more details, see the
description of the BCR3 register.
(a) Burst Read
Figure 10.31 is the timing chart for burst-read operations. In the example shown below,
two synchronous DRAMs of 512k × 16 bits × 2 banks are assumed to be connected and
used with a 32-bit data width and a burst length of 8. After the Tr cycle which outputs an
ACTV command, a READA command is issued in cycle Tc1. During cycles Td1 to Td8,
the read data are fetched at the rising edges of the off-chip command clock (CKIO). Tpc is
the cycle used to wait for completion of auto-precharging, which is triggered by the
READA command, in the synchronous DRAM. During this cycle, no new command that
accesses the same bank can be issued. In this LSI, bits TPC2 to TPC0 in MCR are used to
determine the number of Tpc cycles, and no commands are issued for the synchronous
DRAM during these cycles.
Figure 10.31 shows an example of the basic timing of a burst-read. To allow the connection
of a lower-speed DRAM, the bits in WCR2 and MCR can be set to increase the number of
cycles. Bits RCD1 and RCD0 in MCR can be used to specify the number of cycles from
the ACTV command output cycle Tr to the READA command output cycle Tc1, where
setting values of 1, 2, or 3 correspond to 2, 3, or 4 cycles, respectively. When two or more
cycles are specified, the Trw cycle for issuing of NOP commands to the synchronous
DRAM is inserted between the Tr and Tc cycles. Bits A2W2 to A2W0 and A3W2 to
A3W0 in WCR2 can be used to set the number of cycles from the READA command
output cycle Tc1 to cycle Td1 where the first read data is received. The number of cycles
from 1 to 5 is specifiable independently for areas 2 and 3. Note that this number of cycles
is equal to the number of CAS latency cycles of the synchronous DRAM.
Rev. 1.0, 02/03, page 324 of 1294