SH7760 Datasheet, PDF (542/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 14.3 Register Configuration (2)
Register Name
Abbrev.
Power-on
Reset by
RESET Pin/
WDT/H-UDI
Manual
Reset by
RESET
Pin/WDT/
Multiple
Exception
Standby
Sleep
by
by Sleep
Software/
Instruction/ by
Each
Deep Sleep Hardware Module
Standby control register
STBCR
H’00
Retained Retained
* Retained
Standby control register 2 STBCR2
H’00
Retained Retained
Retained
Clock stop register 00
CLKSTP00
H’0000 0000 Retained Retained
Retained
Clock stop clear register 00 CLKSTPCLR00 

Retained
Retained
Notes: * After exiting hardware standby mode, this LSI enters the power-on reset state caused
by the RESET pin.
14.2.1 Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the power-down mode status.
Bit: 7
6
5
4
3
2
1
0
STBY ^-
- _MSTP4 - _MSTP2 -
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R
R R/W R R/W R
R
Bit
Bit Name Initial Value R/W Description
7
STBY
0
R/W Standby
Specifies a transition to software standby mode.
0: Transition to sleep mode on execution of
SLEEP instruction
1: Transition to software standby mode on
execution of SLEEP instruction
6, 5 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.0, 02/03, page 492 of 1294