SH7760 Datasheet, PDF (194/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
1
WT
0
R/W Write-Through Mode
Indicates the P0, U0, and P3 area cache write
mode. When address translation is performed,
the value of the WT bit in the page management
information has priority.
0: Copy-back mode
1: Write-through mode
0
OCE
0
R/W OC Enable Bit
Selects whether the OC is used. Note however
when address translation is performed, the OC
cannot be used unless the C bit in the page
management information is also 1.
0: OC not used
1: OC used
7.2.2 Queue Address Control Register 0 (QACR0)
QACR0 can be accessed in longwords from H'FF00 0038 in the P4 area and from H'1F00 0038 in
area 7. QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is
off.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
AREA0
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R
R
Bit
Bit Name
31 to 5 
4 to 2 AREA0
1, 0

Initial Value R/W Description

R
Reserved
These bits are always read as 0. The write value
should always be 0.

R/W When the MMU is off, these bits generate external
address bits [28:26] for SQ0.

R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.0, 02/03, page 144 of 1294