SH7760 Datasheet, PDF (266/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

9.3.6 Interrupt Mask Clear Registers 00, 04 (INTMSKCLR00, INTMSKCLR04)
INTMSKCLR00 and INTMSKCLR04 are 32-bit read-only registers that clear the masking of
individual interrupt requests.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: W W W W W W W W W W W W W W W W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: W W W W W W W W W W W W W W W W
Bit
Bit Name
31 to 0 —
Initial Value R/W
—
W
Description
Interrupt Mask Clear 31 to 0
Each bit selects whether or not to clear the
masking of the interrupt source that corresponds
to that bit. For the correspondence between the
bits and interrupt sources, see table 9.5.
0: Masking of corresponding interrupt is not
changed
1: Masking of corresponding interrupt is cleared
Rev. 1.0, 02/03, page 216 of 1294