SH7760 Datasheet, PDF (437/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

DMARSRB
Bit
Bit Name
31
CH4WEN
30
CH4RS6
29
CH4RS5
28
CH4RS4
27
CH4RS3
26
CH4RS2
25
CH4RS1
24
CH4RS0
23
CH5WEN
22
CH5RS6
21
CH5RS5
20
CH5RS4
19
CH5RS3
18
CH5RS2
17
CH5RS1
16
CH5RS0
15
CH6WEN
14
CH6RS6
13
CH6RS5
12
CH6RS4
11
CH6RS3
10
CH6RS2
9
CH6RS1
8
CH6RS0
7
CH7WEN
6
CH7RS6
5
CH7RS5
4
CH7RS4
3
CH7RS3
2
CH7RS2
1
CH7RS1
0
CH7RS0
Note: n = 4 to 7
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/(W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)
R/W
R/W
R/W
R/W
R/(W)
R/(W)
R/W
R/(W)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)
R/W
R/W
R/W
R/W
R/(W)
R/(W)
R/W
Description
CHnRS6 to CHnRS0 specify transfer request sources to
each channel. DMARSRB bits are allocated to channels
0 to 3. When writing to the CHnRS6 to CHnRS0 bits for
each channel, simultaneously write 1 to the CHnWEN
bit. Clearing the CHnWEN bit to 0 will not change the
values in the CHnRS6 to CHnRS0 bits of each channel
and retain the previous values. The CHnWEN bit is
write-enabled, but it does not retain the written value and
is always read as 0.
CHnRS[6:0]
H'00: Unused or auto-request, TMU input capture
interrupt
H'10: DREQ0*¹
H'11: DREQ1*¹
H'12: DREQ2*¹
H'13: DREQ3*¹
H'20: SCIF(0) Transmit-data-empty
H'21: SCIF(0) Receive-data-full
H'22: SCIF(1) Transmit-data-empty
H'23: SCIF(1) Receive-data-full
H'24: SCIF(2) Transmit-data-empty
H'25: SCIF(2) Receive-data-full
H'26: HSPI Transmit data
H'27: HSPI Receive data
H'28: SIM Transmit data empty
H'29: SIM Receive-data-full
H'2B: MMC FIFO ready
H'2C: ADC AD conversion end data transfer
H'2D: Setting prohibited
H'2E: Setting prohibited
H’7F: --*²
Other than above: Setting prohibited
Note:*1 This setting is valid only in DMABRG mode. It
is invalid in external request 2-channel mode
(channels 2 to 7 cannot accept external
requests).
*2 Use this setting when the DMA transfer is
complete with the request in DMAC retained
(DMARCR.REXn = 1). See (3) Notes on
Ending Transfer in section 11.4.6, Ending DMA
Transfer.
Rev. 1.0, 02/03, page 387 of 1294