SH7760 Datasheet, PDF (115/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 4.5 Logic Operation Instructions
Instruction
Operation
Instruction Code
Privileged T Bit
AND Rm,Rn
Rn & Rm → Rn
0010nnnnmmmm1001 —
—
AND #imm,R0
R0 & imm → R0
11001001iiiiiiii —
—
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm → (R0 + 11001101iiiiiiii —
—
GBR)
NOT Rm,Rn
~Rm → Rn
0110nnnnmmmm0111 —
—
OR Rm,Rn
Rn | Rm → Rn
0010nnnnmmmm1011 —
—
OR #imm,R0
R0 | imm → R0
11001011iiiiiiii —
—
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm → (R0 + GBR)11001111iiiiiiii —
TAS.B @Rn
When (Rn) = 0, 1 → T
0100nnnn00011011 —
Otherwise, 0 → T
In both cases, 1 → MSB of (Rn)
Test result
TST Rm,Rn
Rn & Rm; when result = 0,
1→T
Otherwise, 0 → T
0010nnnnmmmm1000 —
Test result
TST #imm,R0
R0 & imm; when result = 0,
1→T
Otherwise, 0 → T
11001000iiiiiiii —
Test result
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm; when result 11001100iiiiiiii —
= 0, 1 → T
Otherwise, 0 → T
Test result
XOR Rm,Rn
Rn ∧ Rm → Rn
0010nnnnmmmm1010 —
—
XOR #imm,R0
R0 ∧ imm → R0
11001010iiiiiiii —
—
XOR.B #imm,@(R0,GBR) (R0 + GBR) ∧ imm → (R0 + 11001110iiiiiiii —
—
GBR)
Rev. 1.0, 02/03, page 65 of 1294