SH7760 Datasheet, PDF (713/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

access may overwrite the valid data still held in the receive data register. However, this can be
avoided by using the SAR status bit. The software should reset the SAR bit to 0 (if it is set to
1) only after completing a read from the receive data register. Then the receive data register
will not be overwritten.
(5) Writing to ICTXD and the TDFE Flag (FIFO Buffer Mode)
The TDFE flag of ICFSR is set to 1 when the byte count in ICTXD is equal to or smaller than
the transmit trigger byte count by TTRG1 and TTRG0 bits of ICFCR. After TDFE is set, the
transmit data can be written for the number of empty bytes in ICTXD. This allows efficient
continuous transmission. When the byte count in ICTXD is below the transmit trigger count,
the TDFE flag is automatically set to 1 even if the flag is cleared to 0. Accordingly, clear the
TDFE flag to 0 only when the byte count in ICTXD exceeds the transmit trigger byte count.
The transmit byte count in ICTXD can be informed by ICTFDR.
(6) Reading from ICRXD and the RDF Flag (FIFO Buffer Mode)
The RDF flag of ICFSR is set to 1 when the receive byte count in ICRXD reaches the receive
trigger byte count by RTRG3 to RTRG0 bits of ICFCR. After RDF is set, the receive data for
the trigger byte count can be read from ICRXD. This allows efficient continuous reception.
When the byte count in ICRXD is equivalent to or greater than the trigger count after a read,
the RDF flag is cleared to 0 even if it is set to 1 again. Accordingly, read the RDF flag as 1 and
then clear it to 0 after reading all data. The receive byte count in ICRXD can be informed by
ICRFDR.
19.4.5 I²C Bus Data Format
Figure 19.2 shows the bus timing of the I²C bus interface. Table 19.4 describes legend in figure
19.2.
SDA
SCL
1–7 8 9
1–7
8 9 1–7 8 9
S
SLA R/W A
DATA
P
A
DATA A/A
Figure 19.2 I²C Bus Timing
Rev. 1.0, 02/03, page 663 of 1294