SH7760 Datasheet, PDF (30/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 7.2 Configuration of Instruction Cache ...........................................................................140
Figure 7.3 Configuration of Write-Back Buffer .........................................................................148
Figure 7.4 Configuration of Write-Through Buffer .................................................................... 148
Figure 7.5 Memory-Mapped IC Address Array..........................................................................152
Figure 7.6 Memory-Mapped IC Data Array ...............................................................................153
Figure 7.7 Memory-Mapped OC Address Array ........................................................................154
Figure 7.8 Memory-Mapped OC Data Array..............................................................................155
Figure 7.9 Memory-Mapped IC Address Array..........................................................................157
Figure 7.10 Memory-Mapped IC Data Array .............................................................................158
Figure 7.11 Memory-Mapped OC Address Array ......................................................................159
Figure 7.12 Memory-Mapped OC Data Array............................................................................160
Figure 7.13 Store Queue Configuration......................................................................................161
Section 8 Exceptions
Figure 8.1 Instruction Execution and Exception Handling .........................................................171
Figure 8.2 Example of General Exception Acceptance Order ....................................................172
Section 9 Interrupt Controller (INTC)
Figure 9.1 Block Diagram of INTC............................................................................................204
Figure 9.2 Example of IRL Interrupt Connection.......................................................................218
Figure 9.3 Interrupt Operation Flowchart ...................................................................................226
Section 10 Bus State Controller (BSC)
Figure 10.1 Block Diagram of BSC............................................................................................231
Figure 10.2 Correspondence between Virtual Address Space and Off-chip Memory Space......234
Figure 10.3 Off-chip Memory Space Allocation ........................................................................236
Figure 10.4 Example of RDY Sampling Timing ........................................................................253
Figure 10.5 Write to RTCSR, RTCNT, RTCOR, or RFCR........................................................279
Figure 10.6 Basic Timing of SRAM Interface............................................................................292
Figure 10.7 Example of 32-Bit Data Width SRAM Connection ................................................293
Figure 10.8 Example of 16-Bit Data Width SRAM Connection ................................................294
Figure 10.9 Example of 8-Bit Data Width SRAM Connection ..................................................294
Figure 10.10 SRAM Interface Wait Timing (Software Wait Only)............................................295
Figure 10.11 SRAM Interface Wait Timing (Wait Cycle Insertion by RDY Signal) .................296
Figure 10.12 SRAM Interface Wait State Timing (Read Strobe Negate Timing Setting;
AnS = 1, AnW = 011, AnH = 10)..........................................................................297
Figure 10.13 DCK, BS2, and CS1 Timing when Reading SRAM Interface
(DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3,
CSH[1:0] in WCR4 = 10, Three Wait Cycles) ......................................................298
Figure 10.14 DCK, BS2, and CS1 Timing when Writing to SRAM Interface
(DCKDR = H'0002, A1RDH = 1 and A1H[1:0] = 10 in WCR3,
CSH[1:0] in WCR4 = 10, Three Wait Cycles) ......................................................299
Figure 10.15 Connection Example of Synchronous DRAM with 32-Bit Data Width
(Area 3).................................................................................................................301
Rev. 1.0, 02/03, page xxviii of xlviii