SH7760 Datasheet, PDF (260/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
14
MAI
13 to 10 —
9
NMIB
8
NMIE
7
IRLM
Initial Value R/W
0
R/W
All 0
—
0
R/W
0
R/W
0
R/W
Description
NMI Interrupt Mask
Specifies whether or not all interrupts are to be
masked while the NMI pin input level is low,
irrespective of the BL bit in SR of the CPU. NMI
interrupts are accepted in normal operation and in
sleep mode. In standby mode, all interrupts are
masked, and standby is not cleared, while the
NMI pin is low.
0: Interrupts enabled even while NMI pin is low
1: Interrupts disabled while NMI pin is low
Reserved
These bits are always read as 0.The write value
should always be 0.
NMI Block Mode
Specifies whether an NMI request is to be held
pending or detected immediately while the BL bit
in SR of the CPU is set to 1.
If interrupt requests are enabled while the BL bit
is 1, the previous exception information will be
lost, and so must be saved beforehand. This bit is
cleared automatically by NMI acceptance.
0: NMI interrupt requests held pending while the
BL bit in SR is set to 1
1: NMI interrupt requests detected while the BL
bit in SR is set to 1
NMI Edge Select
Specifies whether the falling or rising edge of the
interrupt request signal to the NMI pin is detected.
0: Interrupt request detected on falling edge of
NMI input
1: Interrupt request detected on rising edge of
NMI input
IRL Pin Mode
Specifies whether pins IRL3 to IRL0 are to be
used as level-encoded interrupt requests or as
four independent interrupt requests.
0: IRL pins used as level-encoded interrupt
requests
1: IRL pins used as four independent interrupt
requests (level-sensing IRQ mode)
Rev. 1.0, 02/03, page 210 of 1294