SH7760 Datasheet, PDF (356/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(5) Burst Write
The timing chart for a burst write is shown in figure 10.18. In this LSI, a burst write occurs
only in the event of 32-byte transfer. In a burst write operation, the WRIT command is issued
in cycle Tc1 following the Tr cycle where the ACTV command is output, and then 4 cycles
later, the WRITA command is issued. In the write cycle, the write data is output at the same
time as the write command. For the write with auto-precharge command, precharging of the
relevant bank is performed in the synchronous DRAM after completion of the write command,
and therefore no command can be issued for the same bank until precharging is completed.
Consequently, in addition to the precharge wait cycle Tpc used in a read access, cycle Trwl is
also added as a wait cycle until precharging is started following the write command for
delaying issuance of a new command for the synchronous DRAM during this period. Bits
TRWL2 to TRWL0 in MCR can be used to specify the number of Trwl cycles. Access is
started from 16-byte boundary data, and 32-byte boundary data is written in wraparound mode.
DACK is asserted two cycles before the data write cycle.
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
Tr Trw Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Trw1 Trw1 Tpc
Row
Row
H/L
H/L
Row
c1
c5
D31–D0
(write)
BS
CKE
DACKn
(SA: IO → memory)
c1 c2 c3 c4 c5 c6 c7 c8
Note: For DACKn, an example is shown where CHCRn.AL (acknowledge level) = 0 for the DMAC.
Figure 10.18 Basic Timing for Synchronous DRAM Burst Write
Rev. 1.0, 02/03, page 306 of 1294