SH7760 Datasheet, PDF (33/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 11.19 Dual Address Mode/Burst Mode in External Request 2-Channel Mode
External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) ....429
Figure 11.20 Dual Address Mode/Burst Modes in DMABRG Mode
External Bus → External Bus/DREQ (Edge Detection), DACK (Read Cycle) ....430
Figure 11.21 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
External Bus → External Device/ DREQ (Level Detection).................................431
Figure 11.22 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
External Bus → External Device/ DREQ (Level Detection).................................432
Figure 11.23 Single Address Mode/Cycle Steal Mode in External Request 2-Channel Mode
External Bus → External Device/ DREQ (Edge Detection)..................................433
Figure 11.24 Single Address Mode/Cycle Steal Mode in DMABRG Mode
External Bus → External Device/ DREQ (Edge Detection)..................................434
Figure 11.25 Single Address Mode/Burst Mode in External Request 2-Channel Mode
External Bus → External Device/ DREQ (Level Detection).................................435
Figure 11.26 Single Address Mode/Burst Mode in DMABRG Mode External Bus →
External Device/ DREQ (Level Detection) ...........................................................436
Figure 11.27 Single Address Mode/Burst Mode in External Request 2-Channel Mode
External Bus → External Device/ DREQ (Edge Detection)..................................437
Figure 11.28 Single Address Mode/Burst Mode in DMABRG Mode
External Bus → External Device/ DREQ (Edge Detection)..................................438
Figure 11.29 Single Address Mode/Burst Mode in External Request 2-Channel Mode
External Device → External Bus/ DREQ (Level Detection)/32 Byte
Block Transfer (Bus Width: 32 bits, SDRAM: row hit write) ...............................439
Figure 11.30 Single Address Mode/Burst Mode in DMABRG Mode
External Device → External Bus/ DREQ (Level Detection)/32 Byte
Block Transfer (Bus Width: 32 bits, SDRAM: row hit write) ...............................440
Figure 11.31 Configuration of DMA for HAC/SSI ....................................................................449
Figure 11.32 Example of HAC DMA Transfer Operation Flow ................................................451
Figure 11.33 Example of SSI DMA Transfer Operation Flow ...................................................452
Figure 11.34 Forced Termination and Resume Procedures for DMA Audio Transfer ...............454
Figure 11.35 HAC/SSI DMA Transfer Operation Flow Using an Interrupt...............................455
Figure 11.36 8-Bit Data Transfer for SSI ...................................................................................457
Figure 11.37 16-Bit Data Transfer for HAC/SSI ........................................................................457
Figure 11.38 Example of LCDC Data Transfer Flow.................................................................458
Figure 11.39 DMA Transfer Flow Shared Memory ↔ Synchronous DRAM............................459
Figure 11.40 Bus Arrangement for Data Alignment....................................................................460
Section 12 Clock Pulse Generator (CPG)
Figure 12.1 Block Diagram of CPG ...........................................................................................466
Figure 12.2 Points for Attention when Using Crystal Resonator................................................479
Figure 12.3 Points for Attention when Using PLL Oscillation Circuit.......................................480
Section 13 Watchdog Timer (WDT)
Figure 13.1 Block Diagram of WDT ..........................................................................................481
Rev. 1.0, 02/03, page xxxi of xlviii