SH7760 Datasheet, PDF (1149/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

31.2.7 Break Data Register B (BDRB)
BDRB is a 32-bit readable/writable register that specifies the data (bits 31 to 0) to be used in the
channel B break conditions.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDB15 BDB14 BDB13 BDB12 BDB11 BDB10 BDB9 BDB8 BDB7 BDB6 BDB5 BDB4 BDB3 BDB2 BDB1 BDB0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
BDB31 to
BDB0
Initial Value R/W
—
R/W
Description
Break Data B
These bits store the data (bits 31 to 0) to be used
in the channel B break conditions.
31.2.8 Break Data Mask Register B (BDMRB)
BDMRB is a 32-bit readable/writable register that specifies which bits of the break data set in
BDRB are to be masked. When the value of the data bus is included in the break conditions, its
operand size should be specified. When the byte size is specified as an operand size, the same data
should be specified to bits 15 to 8 and bits 7 to 0 in both BDRB and BDMRB.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB8
Initial value: -
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BDMB7 BDMB6 BDMB5 BDMB4 BDMB3 BDMB2 BDMB1
-
-
-
-
-
-
-
R/W R/W R/W R/W R/W R/W R/W
BDMB0
-
R/W
Rev. 1.0, 02/03, page 1099 of 1294