SH7760 Datasheet, PDF (882/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
8
FFEN
0
R/W FIFO Mode Enable
Enables or disables the FIFO mode. When FIFO
mode is enabled two 8-entry deep FIFOs are
made available, one for transmit data and one for
receive data. These FIFOs are read and written
via SPTBR and SPRBR. When FIFO mode is
disabled the SPTBR and SPRBR are used
directly so new data must be written to SPTBR
and read from SPRBR for each and every
transfer. FIFO mode must be disabled if DMA
requests are also going to be used to service
SPTBR and SPRBR.
0: FIFO mode disabled
1: FIFO mode enabled
7
LMSB
0
R/W LSB/MSB First Control
0: Data is transmitted and received most
significant bit (MSB) first.
1: Data is transmitted and received least
significant bit (LSB) first.
6
CSV
1
R/W Chip Select Value
Controls the value output from the chip select
when the HSPI is a master and the chip select
generation has been selected.
0: Chip select output is low.
1: Chip select output is high.
5
CSA
0
R/W Automatic/Manual Chip Select
0: Chip select output is automatically generated
during data transfer.
1: Chip select output is manually controlled, with
its value being determined by the CSV bit.
4
TFIE
0
R/W Transmit Complete Interrupt Enable
0: Transmit complete interrupt disabled
1: Transmit complete interrupt enabled
3
ROIE
0
R/W Receive Overrun Occurred / Warning Interrupt
Enable
0: Receive overrun occurred / warning interrupt
disabled
1: Receive overrun occurred / warning interrupt
enabled
Rev. 1.0, 02/03, page 832 of 1294