SH7760 Datasheet, PDF (103/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Since approximate-value computations are performed to enable high-speed computation, the
inexact exception (I) bit in both the FPU exception cause field and flag field are always set to 1
when an FTRV instruction is executed. Therefore, if the I bit is set in the FPU exception enable
field, FPU exception handling will be executed. It is not possible to check all data types in the
registers beforehand when executing an FTRV instruction. If the V bit is set in the FPU exception
enable field, FPU exception handling will be executed.
FRCHG: This instruction modifies banked registers. For example, when the FTRV instruction is
executed, matrix elements must be set in an array in the background bank. However, to create the
actual elements of a translation matrix, it is easier to use registers in the foreground bank. When
the LDS instruction is used on FPSCR, this instruction takes four to five cycles in order to
maintain the FPU state. With the FRCHG instruction, the FR bit in FPSCR can be changed in one
cycle.
3.6.2 Pair Single-Precision Data Transfer
In addition to the powerful new geometric operation instructions, this LSI also supports high-
speed data transfer instructions.
When the SZ bit is 1, this LSI can perform data transfer by means of pair single-precision data
transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
• FSCHG
This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between use
and non-use of pair single-precision data transfer.
3.7 Notes on programming
When the SZ bit is 1 and big-endian mode is used, FMOV can be used for a double-precision
floating-point load or store. In little-endian mode, a double-precision floating-point load or store
requires execution of two 32-bit data size operations with the SZ bit in FPSCR cleared to 0.
Rev. 1.0, 02/03, page 53 of 1294