SH7760 Datasheet, PDF (1278/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
Bank
TRr1
TRr2
TRr3
TRr4
TRrw
TRr5
Trc
Trc
Trc
t_AD
t_AD
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
t_CSD
t_CSD
t_CSD
t_RWD
t_RASD
t_RASD
t_RASD
t_CASD2 t_CASD2 t_CASD2
t_DQMD
t_RWD
t_CASD2
t_CSD
t_RASD
t_DQMD
D31-D0
(write)
BS
t_WDD
t_WDD
t_BSD
CKE
DACKn
t_DACD
t_DACD
NOTES:
IO : Dack device
SA : Single address DMA transfer
DA : Dual address DMA transfer
DACK set to active-high
Figure 33.36 Synchronous DRAM Bus Cycle: Auto-Refresh (TRAS=1, TRC[2:0]=001)
Rev. 1.0, 02/03, page 1228 of 1294