SH7760 Datasheet, PDF (470/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CPU
DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1
CH0
CH1
CH0
CPU
CPU
DMAC channel 1
burst mode
DMAC channel 0 and
channel 1 round robin
mode
DMAC channel 1
burst mode
Priority order:
Channel 0:
Channel 1:
Round robin mode
Cycle steal mode
Burst mode (edge-sensing)
Figure 11.12 Bus Handling with Two DMAC Channels Operating
CPU
11.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing
(1) Number of Bus Cycles
The number of bus cycles when the DMAC is the bus master is controlled by the bus state
controller (BSC) just as it is when the CPU is the bus master. See section 10, Bus State
Controller (BSC), for details.
(2) DREQ Pin Sampling Timing
In external request mode, the DMAC samples the DREQ pin at the rising edge of a CKIO
clock signal. When detecting a DREQ input, the DMAC generates a bus cycle and performs
DMA transfer after four CKIO cycles at the earliest.
In the case of DREQ falling edge sampling, the DMAC detects a DREQ input after two CKIO
cycles (in the case of low-level sampling, one CKIO cycle).
The second and subsequent DREQ sampling operations are performed one cycle after the start
of the first DMAC transfer bus cycle (in the case of external request 2-channel mode and
single address mode).
DRAK is output for one cycle only, once each time DREQ is detected, regardless of the
transfer mode or DREQ detection method. In the case of burst mode edge detection, DREQ is
sampled in the first cycle only, and so DRAK is output in the first cycle only.
(3) Operation
• Cycle Steal Mode
In cycle steal mode, The DREQ sampling timing differs for dual address mode and single
address mode, and for level detection and edge detection of DREQ.
Rev. 1.0, 02/03, page 420 of 1294