SH7760 Datasheet, PDF (1281/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

CKIO
Bank
TRp1 TRp2 TRp3 TRp4
TMw TMw2 TMw3 TMw4 TMw5
t_AD
t_AD
t_AD
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31-D0
(write)
BS
CKE
DACKn
t_RWD
t_RASD
t_CASD2
t_DQMD
t_WDD
t_DACD
t_CSD t_CSD
t_RWD
t_RASD
t_CASD2
t_CASD2
t_CSD
t_RWD
t_RASD
t_CASD2
t_DQMD
t_WDD
t_BSD
t_DACD
NOTES:
IO : Dack device
SA : Single address DMA transfer
DA : Dual address DMA transfer
DACK set to active-high
Figure 33.39 Synchronous DRAM Bus Cycle: Mode Register Setting (SET)
Rev. 1.0, 02/03, page 1231 of 1294