SH7760 Datasheet, PDF (965/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

26.3.2 Command Type Register (CMDTYR)
CMDTYR is an 8-bit readable/writable register that specifies the command format in conjunction
with RSPTYR. Bits TY1 and TY0 specify the existence and direction of transfer data, and bits
TY4 to TY2 specify the additional settings. All of bits TY4 to TY2 should be cleared to 0 or only
one of them should be set to 1. Bits TY4 to TY2 can only be set to 1 if the corresponding settings
in TY1 and TY0 allow that setting.
Bit: 7
6
5
4
3
2
1
0
-
-
- _{TY4 TY3 TY2 TY1 TY0}
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W
Bit
7 to 5
4
3
2
1
0
Bit
Name

TY4
TY3
TY2
TY1
TY0
Initial
Value
All 0
0
0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Type 4
Set this bit to 1 when specifying the CMD12 command.
Bits TY1 and TY0 should be set to 00.
R/W Type 3
Set this bit to 1 when specifying stream transfer. Bits
TY1 and TY0 should be set to 01 or 10.
The command sequence of the stream transfer
specified by this bit ends when it is aborted by the
CMD12 command.
R/W Type 2
Set this bit to 1 when specifying multiblock transfer.
Bits TY1 and TY0 should be set to 01 or 10.
The command sequence of the multiblock transfer
specified by this bit ends when it is aborted by the
CMD12 command.
R/W Types 1 and 0
R/W These bits specify the existence and direction of
transfer data.
00: A command without data transfer
01: A command with read data reception
10: A command with write data transmission
11: Setting prohibited
Rev. 1.0, 02/03, page 915 of 1294