SH7760 Datasheet, PDF (114/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Instruction
Operation
Instruction Code
Privileged T Bit
CMP/STR Rm,Rn
When any bytes are equal,
1→T
Otherwise, 0 → T
0010nnnnmmmm1100 —
Comparison
result
DIV1
Rm,Rn
1-step division (Rn ÷ Rm)
0011nnnnmmmm0100 —
Calculation
result
DIV0S Rm,Rn
MSB of Rn → Q,
MSB of Rm → M, M^Q → T
0010nnnnmmmm0111 —
Calculation
result
DIV0U
0 → M/Q/T
0000000000011001 —
0
DMULS.L Rm,Rn
Signed, Rn × Rm → MAC,
0011nnnnmmmm1101 —
—
32 × 32 → 64 bits
DMULU.L Rm,Rn
Unsigned, Rn × Rm → MAC, 0011nnnnmmmm0101 —
—
32 × 32 → 64 bits
DT
Rn
Rn – 1 → Rn; when Rn = 0,
1→T
When Rn ≠ 0, 0 → T
0100nnnn00010000 —
Comparison
result
EXTS.B Rm,Rn
Rm sign-extended from
0110nnnnmmmm1110 —
—
byte → Rn
EXTS.W Rm,Rn
Rm sign-extended from
0110nnnnmmmm1111 —
—
word → Rn
EXTU.B Rm,Rn
Rm zero-extended from
0110nnnnmmmm1100 —
—
byte → Rn
EXTU.W Rm,Rn
Rm zero-extended from
0110nnnnmmmm1101 —
—
word → Rn
MAC.L @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → 0000nnnnmmmm1111 —
—
MAC
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
MAC.W @Rm+,@Rn+ Signed, (Rn) × (Rm) + MAC → 0100nnnnmmmm1111 —
—
MAC
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
MUL.L Rm,Rn
Rn × Rm → MACL
32 × 32 → 32 bits
0000nnnnmmmm0111 —
—
MULS.W Rm,Rn
Signed, Rn × Rm → MACL
0010nnnnmmmm1111 —
—
16 × 16 → 32 bits
MULU.W Rm,Rn
Unsigned, Rn × Rm → MACL 0010nnnnmmmm1110 —
—
16 × 16 → 32 bits
NEG
Rm,Rn
0 – Rm → Rn
0110nnnnmmmm1011 —
—
NEGC Rm,Rn
0 – Rm – T → Rn, borrow → T 0110nnnnmmmm1010 —
Borrow
SUB
Rm,Rn
Rn – Rm → Rn
0011nnnnmmmm1000 —
—
SUBC Rm,Rn
Rn – Rm – T → Rn, borrow → T 0011nnnnmmmm1010 —
Borrow
SUBV
Rm,Rn
Rn – Rm → Rn, underflow → T 0011nnnnmmmm1011 —
Underflow
Rev. 1.0, 02/03, page 64 of 1294