SH7760 Datasheet, PDF (1071/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit Name Value R/W
Description
1
CH1
0
0
CH0
0
R/W
Channel Select
R/W
These bits select the analog input channels together with
the MDS1 bits.
Select the input channels after clearing the ADST bit to 0.
Single Mode
(MDS1 = 0):
Multi Mode or Scan
Mode (MDS1 = 1):
00: AN0
01: AN1
10: AN2
11: AN3
00: AN0
01: AN0 and AN1
10: AN0 to AN2
11: AN0 to AN3
Note: * Only 0 can be written for clearing the flag.
29.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has three
operating modes: single mode, multi mode, and scan mode. To avoid malfunction, switch
operating modes while the ADST bit of ADCSR is 0. Changing operating modes and channels and
setting the ADST bit can be performed simultaneously.
29.4.1 Single Mode
In single mode, an analog input for the specified channel is converted once as shown below.
1. A/D conversion of the selected channel starts when the ADST bit of ADCSR is set to 1 by
software or an external trigger input. The ADST bit holds 1 during A/D conversion and is
automatically cleared to 0 when the A/D conversion ends.
2. When A/D conversion ends, the conversion results are transmitted to the A/D conversion data
register that corresponds to the channel.
3. When A/D conversion ends, the ADF bit of ADCSR is set to 1. If the ADIE bit in ADCSR is
also set to 1, an ADI interrupt is requested at this time.
4. Writing 0 to the ADF bit after reading ADF = 1 clears the ADF bit.
Rev. 1.0, 02/03, page 1021 of 1294