SH7760 Datasheet, PDF (1148/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

31.2.6 Break Bus Cycle Register B (BBRB)
BBRB is a 16-bit readable/writable register that specifies three conditions from among the channel
B break conditions: instruction access/operand access, read/write, and operand size.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
- SZB2 IDB1 IDB0 RWB1 RWB0 SZB1 SZB0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name Initial Value R/W
15 to 7 —
All 0
R
5
IDB1
0
R/W
4
IDB0
0
R/W
3
RWB1 0
R/W
2
RWB0 0
R/W
6
SZB2
0
R/W
1
SZB1
0
R/W
0
SZB0
0
R/W
Note: x: Don't care
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Instruction Access/Operand Access Select B
These bits specify whether an instruction access cycle
or an operand access cycle is used as the bus cycle
in the channel B break conditions.
00: Condition comparison is not performed
01: Instruction access cycle is used as break condition
10: Operand access cycle is used as break condition
11: Instruction access cycle or operand access cycle
is used as break condition
Read/Write Select B
These bits specify whether a read cycle or write cycle
is used as the bus cycle in the channel B break
conditions.
00: Condition comparison is not performed
01: Read cycle is used as break condition
10: Write cycle is used as break condition
11: Read cycle or write cycle is used as break
condition
Operand Size Select B
These bits select the operand size of the bus cycle
used as a channel B break conditions.
000: Operand size is not included in break conditions
001: Byte access is used as break condition
010: Word access is used as break condition
011: Longword access is used as break condition
100: Quadword access is used as break condition
101: Setting prohibited
11x: Setting prohibited
Rev. 1.0, 02/03, page 1098 of 1294