SH7760 Datasheet, PDF (233/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(2) Instruction TLB Miss Exception
• Source: Address mismatch in ITLB address comparison
• Transition address: VBR + H'0000 0400
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
The PC and SR contents for the instruction at which this exception occurred are saved in SPC
and SSR. The R15 contents at this time are saved in SGR.
Exception code H'040 is set in EXPEVT. The BL, MD, and RB bits are set to 1 in SR, and a
branch is made to PC = VBR + H'0400.
To speed up TLB miss processing, the offset is separate from that of other exceptions.
ITLB_miss_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 0040;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0400;
}
Rev. 1.0, 02/03, page 183 of 1294