SH7760 Datasheet, PDF (371/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

(10) Power-On Sequence
To use synchronous DRAM, the mode must first be set after power is supplied. To initialize
synchronous DRAM correctly, the bus state controller registers must first be set, and then
writing must be performed to the synchronous DRAM mode register. In the synchronous
DRAM mode register setting, the address signal value at that time is latched by a combination
of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller
operates so that the value X is written to the synchronous DRAM mode register by performing
a write to address H'FF90 0000 + X for area 2 synchronous DRAM, and to address H'FF94
0000 + X for area 3 synchronous DRAM. In this operation, the data is ignored, but the mode
write is performed as a byte-size access. To set burst read/burst write, CAS latency 1 to 3,
wrap type = sequential, and burst length 4 or 8, which are supported by this LSI, arbitrary data
is written in byte-size access to the following addresses.
Bus Width
32
32
Burst Length CAS Latency
4
1
2
3
8
1
2
3
Area 2
H'FF90 0048
H'FF90 0088
H'FF90 00C8
H'FF90 004C
H'FF90 008C
H'FF90 00CC
Area 3
H'FF94 0048
H'FF94 0088
H'FF94 00C8
H'FF94 004C
H'FF94 008C
H'FF94 00CC
The MRSET bit in MCR selects whether a precharge all banks command or a mode register
setting command is issued. The timing for the precharge all banks command is shown in figure
10.30(1), and the timing for the mode register setting command is shown in figure 10.30(2).
Before setting the mode register, a 200-µs idle time (this is required for the synchronous
DRAM and varies depending on the memory manufacturer) after power is supplied must be
guaranteed. There is no problem in making the precharge all banks setting immediately if the
reset signal pulse width is greater than this idle time.
First, a precharge all banks (PALL) command is issued in the TRp1 cycle by writing to address
H'FF90 0000 + X or H'FF94 0000 + X while the MRSET bit in MCR is cleared to 0. Next, the
number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must
be executed. This is achieved automatically while performing various kinds of initialization
after the auto-refresh setting is made, but a more accurate way is to change the RTCOR value
only while these dummy cycles are being executed to set a short interval that generates refresh
requests. With simple read or write access, the address counter in the synchronous DRAM
used for auto-refreshing is not initialized, and so the cycle must always be an auto-refresh
cycle. After auto-refreshing has been executed at least the prescribed number of times, a mode
register write command is issued in the TMw1 cycle by setting MCR.MRSET to 1 and writing
to address H'FF90 0000 + X or H'FF94 0000 + X.
Rev. 1.0, 02/03, page 321 of 1294