SH7760 Datasheet, PDF (296/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W Description
14
HIZCNT 0
R/W High Impedance (High-Z) Control
Specifies the state of the RAS and CAS signals in
software standby mode and the bus-released state.
0: The RAS, WEn /DQMn, and RD/CASS/FRAME signals
made to the high-impedance in software standby
mode and the bus-released state
1: The RAS, WEn /DQMn, and RD/CASS/FRAME signals
driven in software standby mode and the bus-released
state
13
A0BST2 0
12
A0BST1 0
11
A0BST0 0
R/W Area 0 Burst ROM Control
R/W These bits specify whether burst ROM interface is used
R/W in area 0. When burst ROM interface is used, they also
specify the number of accesses in a burst. When area 0
is used as an MPX interface area, the settings of these
bits are ignored.
000: Area 0 is accessed as SRAM interface.
001: Area 0 is accessed as burst ROM interface
(4 consecutive accesses). Can be used with 8-, 16-,
or 32-bit bus width
010: Area 0 is accessed as burst ROM interface
(8 consecutive accesses). Can be used with 8-, 16-,
or 32-bit bus width
011: Area 0 is accessed as burst ROM interface
(16 consecutive accesses). Can only be used with
8- or 16-bit bus width. The setting of 32-bit bus width
is prohibited.
100: Area 0 is accessed as burst ROM interface
(32 consecutive accesses). Can only be used with
8-bit bus width
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Rev. 1.0, 02/03, page 246 of 1294