SH7760 Datasheet, PDF (499/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

This LSI
AC97 codec 0
or
I²S codec 0
AC97 codec 1
or
I²S codec 1
HAC(0)
transmit and receive
SSI(0)
transmit or receive
HAC(1)
transmit and receive
SSI(1)
transmit or receive
DMAC
DMABRG
Transmit FIFO (0)
Receive FIFO (0)
Transmit FIFO (1)
Receive FIFO (1)
Peripheral bus
Transfer request
priority control
Specified by IPSELR in PFC
Bus state
controller
External bus
External synchronous DRAM
Memory space
Transfer start address
Half of the transfer size
Transfer end address
Transmit/receive
buffer
2-stage buffer control for audio data is
enabled by using two types of interrupts:
one is generated when half of data has
been transferred and another one is
generated when all data has been transferred.
Figure 11.31 Configuration of DMA for HAC/SSI
Rev. 1.0, 02/03, page 449 of 1294