SH7760 Datasheet, PDF (667/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.3.9 Smart Card Mode Register (SISCMR)
SISCMR is an 8-bit readable/writable register that selects smart card interface functions.
Bit: 7
6
5
- LCB PB
Initial value: 0
0
0
R/W: R R/W R/W
4
3
2
1
0
- SDIR SINV RST SMIF
0
0
0
0
1
R R/W R/W R/W R/W
Bit
Bit Name
7
6 LCB
5 PB
4
3 SDIR
Initial
Value R/W Description
0
R
Reserved
This bit is always read as 0. The write value should always be
0.
0
R/W Last Character
When this bit is set to 1, the guardtime is 2 etu, and the
setting of the guard extension register is invalid.
0: The guardtime is determined by the guard
value
1: The guardtime is 2 etu
register
0
R/W Protocol
Selects the T = 0 or T = 1 protocol.
0: The smart card interface operates according to the T = 0
protocol
1: The smart card interface operates according to the T = 1
protocol
0
R
Reserved
This bit is always read as 0. The write value should also
always be 0.
0
R/W Smart Card Data Transfer Direction
Selects the format for serial/parallel conversion.
0: Transmit the SITDR contents LSB-first
Received data is stored in SIRDR LSB-first.
1: Transmit the SITDR contents MSB-first
Received data is stored in SIRDR MSB-first.
Rev. 1.0,02/03, page 617 of 1294