SH7760 Datasheet, PDF (424/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
28
STC
0
R/W Source Address Wait Control Select
Specifies the CS5 or CS6 space wait cycle control
for the source address when accessing a PCMCIA
interface area.
0: CS5 space wait cycle selection
Settings of bits A5W2 to A5W0 in WCR2 and
bits A5PCW1 and A5PCW0, A5TED2 to
A5TED0, and A5TEH2 to A5TEH0 in PCR are
selected
1: CS6 space wait cycle selection
Settings of bits A6W2 to A6W0 in WCR2 and
bits A6PCW1 and A6PCW0, A6TED2 to
A6TED0, and A6TEH2 to A6TEH0 in PCR are
selected
27
DSA2
0
26
DSA1
0
25
DSA0
0
R/W Destination Address Space Attribute Specification
R/W _{These bits specify the space attribute for the}
R/W _{destination address when accessing a PCMCIA}
interface area. These bits are only valid in the
case of page mapping to PCMCIA connected to
areas 5 and 6.
000: Reserved in PCMCIA access
001: Dynamic bus sizing I/O space
010: 8-bit I/O space
011: 16-bit I/O space
100: 8-bit common memory space
101: 16-bit common memory space
110: 8-bit attribute memory space
111: 16-bit attribute memory space
Rev. 1.0, 02/03, page 374 of 1294