SH7760 Datasheet, PDF (200/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

• Prefetch instruction : PREF @Rn
7.4 Instruction Cache Operation
7.4.1 Read Operation
When the IC is enabled (ICE = 1 in CCR) and instruction fetches are performed by means of an
effective address from a cacheable area, the instruction cache operates as follows:
1. The tag and V bit are read from the cache line indexed by effective address bits [12:5].
2. The tag is compared with bits [28:10] of the address resulting from effective address
translation by the MMU:
• If the tag matches and the V bit is 1
→ 3.
• If the tag matches and the V bit is 0
→ 4.
• If the tag does not match and the V bit is 0
→ 4.
• If the tag does not match and the V bit is 1
→ 4.
3. Cache hit
The data indexed by effective address bits [4:2] is read as an instruction from the data field of
the cache line indexed by effective address bits [12:5].
4. Cache miss
Data is read into the cache line from the external memory space corresponding to the effective
address. Data reading is performed, using the wraparound method, in order from the longword
data corresponding to the effective address, and when the corresponding data arrives in the
cache, the read data is returned to the CPU as an instruction. When reading of one line of data
is completed, the tag corresponding to the effective address is recorded in the cache, and 1 is
written to the V bit.
7.4.2 IC Index Mode
Setting the IIX bit in CCR to 1 enables IC indexing to be performed using bit [25] of the effective
address. This is called IC index mode. In normal mode, with the IIX bit in CCR cleared to 0, IC
indexing is performed using bits [12:5] of the effective address. Using index mode allows the IC
to be handled as two 4-kbyte areas by means of effective address bit [25], providing efficient use
of the cache.
Rev. 1.0, 02/03, page 150 of 1294