SH7760 Datasheet, PDF (1037/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

27.5.2 80-Series 8-Bit Parallel Interface
Figure 27.5 shows the basic read/write sequence for the 80-series 8-bit parallel interface. In the
80-series interface, read operations are limited to the period during which both the MFI-RW/RD
and MFI-CS signals are driven low. Write operations are limited to the period during which both
the MFI-E/WR and the MFI-CS signals are driven low.
The MFI-RS signal has the same function as in the 68-series interface.
MFI-CS
MFI-RS
MFI-E/WR
MFI-RW/RD
MFI-D15 - MFI-D0
Write cycle
WT_D
Read cycle
RD_D
WT_D: Write data
RD_D: Read data
Figure 27.5 Basic Timing of the MFI 80-Series Interface
Rev. 1.0, 02/03, page 987 of 1294