SH7760 Datasheet, PDF (315/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit
Name Value R/W
4n + 1 AnH1 All 1
R/W
4n
AnH0 All 1
R/W
4m + 3 AmRDH All 0
R/W
Note: n = 0 to 6; m = 1 and 4
Description
Area n Data Hold Time
For writing, specifies the number of cycles to be inserted
during the data hold time after the write strobe is
negated. For reading, specifies the number of cycles to
be inserted during the data hold time after the data
sampling timing. Valid only for SRAM interface, byte
control SRAM interface, and burst ROM interface:
Cycles to be inserted during the data hold time
00: 0
01: 1
10: 2
11: 3
Read-Strobe Negate Timing
For reading, these bits specify the timing for the negation
of read strobe. These bits should be cleared to 0 when
byte control SRAM interface is in use.
See figure 10.11.
10.5.8 Wait Control Register 4 (WCR4)
WCR4 is a 32-bit readable/writable register that specifies the negation period for the CS1 signal.
Specifying bits CSH1 and CSH0 can insert the negation cycles from 0 to 3. The WCR4 setting is
valid when the setting of the data hold time (A1H[1:0]) in WCR3 matches the setting of WCR4.
When the settings of WCR3 and WCR4 do not match, correct operation is not guaranteed.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
- CSH1 CSH0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Rev. 1.0, 02/03, page 265 of 1294