SH7760 Datasheet, PDF (724/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Read data from the receive data register.
If next byte is to be the data immediately preceding the last byte transmitted by the slave
device, for the receive interrupt for the byte immediately preceding the last one-byte, i.e.,
MDR interrupt,
(b) Set the master control register 8Ah.
(Set the force stop control bit.)
(c) Reset the MDR bit to 0.
(6) Wait for the end of transmission:
(a) Execute processing of the last byte receive interrupt (MDR), i.e., extract the data and clear
MDR.
(b) Wait for the master device’s event (the MST bit in the master status register).
(c) Reset the MST bit to 0.
19.6.4 Master Transmitter (FIFO Buffer Mode)
Operation example:
1. Set the clock rate to ICCCR.
2. Set the slave address, etc. to ICMAR.
3. Write transmission data to ICTXD (up to 16 bytes can be written).
4. Clear the TDFE flag.
5. ICMCR=H’0000 0009 (set ESG) //ESG=1, MIE=1, MDBS=0. (At this point, the slave address
is output onto I²C bus.)
6. Wait for MAT to be set to 1, and clear ESG, MAT, and MDE to 0. (Transmission data has
been output until FIFO becomes empty.)
7. Wait for TDFE to be set to 1, and write subsequent transmit data to ICTXD.
ICFSR=H’0000 0000 (Clear the flag.)
(Repeat)
8. Wait for TEND to be set to 1, and set FSB to 1.
9. Clear the TEND flag to 0.
19.6.5 Master Receiver (FIFO Buffer Mode)
Operation example:
1. Set the clock rate to ICCCR.
2. Set the slave address, etc. to ICMAR.
3. Set the RDF trigger value to ICFCR.
Rev. 1.0, 02/03, page 674 of 1294