SH7760 Datasheet, PDF (702/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

19.3.8 Master Address Register (ICMAR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
SADD1 SADD1 SADD1 SADD1 SADD1 SADD1 SADD1
_6
_5
_4
_3
_2
_1
_0
STM1
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 8 
Initial Value R/W
All 0
R
7 to 1 SADD1_6 to All 0
R/W
SADD1_0
0
STM1
0
R/W
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
Slave Address
This is the address of the slave the master is to
communicate with.
Slave Transfer Mode
This bit indicates in which mode the slave is to
operate.
This bit sets the operating mode (transmit or
receive mode) of the slave to the external slave
device specified by the slave address (SADD1)
sent from the master. The slave device is
automatically set to the transmit/receive mode by
hardware according to the received STM1 value.
0: Write operation
1: Read operation
19.3.9 Clock Control Register (ICCCR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
SCGD
CDF
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 652 of 1294