SH7760 Datasheet, PDF (85/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W
27 to 16 —
All 0
R
15
FD
0
R/W
14 to 10 —
All 0
R
9
M
—
R/W
8
Q
—
R/W
7
IMASK3 1
R/W
6
IMASK2 1
R/W
5
IMASK1 1
R/W
4
IMASK0 1
R/W
3, 2
—
All 0
R
1
S
—
R/W
0
T
—
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
FPU Disable Bit
A reset clears this bit to 0.
When this bit is set to 1 and an FPU instruction is not
in a delay slot, a general FPU disable exception
occurs. When this bit is set to 1 and an FPU
instruction is in a delay slot, a slot FPU disable
exception occurs. (FPU instructions: H’F***
instructions and LDS (.L)/STS(.L) instructions using
FPUL/FPSCR)
Reserved
These bits are always read as 0. The write value
should always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level Bits
An interrupt whose priority is equal to or less than the
value of the IMASK bits is masked. These bits are not
modified by an interrupt.
Reserved
These bits are always read as 0. The write value
should always be 0.
S Bit
Used by the MAC instruction.
T Bit
Indicates true/false or carry/borrow.
Saved Status Register (SSR): The contents of SR are saved to SSR in the event of an exception
or interrupt.
Saved Program Counter (SPC): The address of an instruction at which an interrupt or exception
occurs is saved to SPC.
Global Base Register (GBR): GBR is referenced as the base address in a GBR-referencing MOV
instruction.
Vector Base Register (VBR): VBR is referenced as the branch destination base address in the
event of an exception or interrupt.
Rev. 0.1, 02/03, page 35 of 1294